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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
4.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
CV DD
CV DDRTC
Supply voltage, Digital Core
Supply voltage, RTC and RTC OSC
60 or 75 MHz
100 or 120 MHz
32.768 KHz
0.998
1.24
0.998
1.05
1.3
1.15
1.43
1.43
V
V
V
Core Supplies
USB_V DD1P3
USB_V DDA1P3
V DDA_ANA
V DDA_PLL
USB_V DDPLL
Supply voltage, Digital USB
Supply voltage, 1.3 V Analog USB
Supply voltage, 1.3 V SAR and Pwr Mgmt
Supply voltage, System PLL
Supply voltage, 3.3 V USB PLL
Supply voltage, I/O, 3.3 V
1.24
1.24
1.24
1.24
2.97
2.97
1.3
1.3
1.3
1.3
3.3
3.3
1.43
1.43
1.43
1.43
3.63
3.63
V
V
V
V
V
V
I/O Supplies
DV DDIO
DV DDEMIF
DV DDRTC
USB_V DDOSC
USB_V DDA3P3
LDOI
Supply voltage, I/O, 2.75 V
Supply voltage, I/O, 2.5 V
Supply voltage, I/O, 1.8 V
Supply voltage, I/O, 3.3 V USB OSC
Supply voltage, I/O, 3.3 V Analog USB PHY
Supply voltage, Analog Pwr Mgmt and LDO Inputs
2.48
2.25
1.65
2.97
2.97
1.8
2.75
2.5
1.8
3.3
3.3
3.02
2.75
1.98
3.63
3.63
3.6
V
V
V
V
V
V
V SS
V SSRTC
USB_V SSOSC
USB_V SSPLL
Supply ground, Digital I/O
Supply ground, RTC
Supply ground, USB OSC
Supply ground, USB PLL
GND
USB_V SSA3P3
USB_V SSA1P3
Supply ground, 3.3 V Analog USB PHY
Supply ground, USB 1.3 V Analog USB PHY
0
0
0
V
USB_V SSREF
V SSA_PLL
USB_V SS1P3
V SSA_ANA
Supply ground, USB Reference Current
Supply ground, System PLL
Supply ground, 1.3 V Digital USB PHY
Supply ground, SAR and Pwr Mgmt
V IH
V IL
V IN
(1)
(1)
High-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except
GPAIN[3:0] pins) (2)
Low-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except
GPAIN[3:0] pins) (2)
Input voltage, GPAIN0 pin (3)
Input voltage, GPAIN[3:1] pins
0.7 * DV DD
-0.3
-0.3
-0.3
DV DD + 0.3
0.3 * DV DD
3.6
V DDA_ANA + 0.3
V
V
V
V
60 or 75
T c
F SYSCLK
Operating case temperature
DSP Operating Frequency (SYSCLK)
Default
(Commercial)
(Industrial)
1.05 V
1.3 V
-10
-40
0
0
70
85
(4)
100 or 120 (4)
°C
°C
MHz
MHz
(1)
(2)
(3)
(4)
DV DD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 2.5 , Terminal Functions .
The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DV DDIO is powered
down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0
(low) and logic 1 (high) are not fixed and depend on DV DDIO .
The GNDON bit in the SARPINCTRL register should be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the
SARCTRL register, when V IN greater than V DDA_ANA .
For the device maximum operating frequency, see Section 6.1.2 , Device and Development-Support Tool Nomenclature .
68
Device Operating Conditions
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